In the field of integrated circuit (IC) technology, MIM capacitors have attracted attention because of their applications in functional circuits such as mixed signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memory (DRAM), and logic operation circuits.
In U.S. Pat. No. 8,143,699, a dual-dielectric MIM capacitor is disclosed. FIG. 1 is a cross-sectional view of an MIM capacitor taught in U.S. Pat. No. 8,143,699. In FIG. 1, the MIM capacitor 10 includes a substrate 12 divided into a first region 100 and a second region 200, in each of which is provided with a capacitor 102 and 202, respectively. The capacitor 102 includes a top electrode 124, a bottom electrode 122 and a dielectric layer 130 sandwiched therebetween. In FIG. 1, the dielectric layer 130 further includes a first dielectric layer 1301 and a second dielectric layer 1302. The capacitor 102 is connected to a circuit 110 underneath by a plug 106. Similarly, the capacitor 202 includes a top electrode 224, a bottom electrode 222 and a dielectric layer 230 sandwiched therebetween, and is connected to a transistor 240 underneath by a plug 206.
Since the two capacitors 102 and 202 of the above MIM capacitor 10 are at the same level to occupy a larger chip area, which is unfavorable to high density IC applications, there is need in providing an MIM capacitor structure with a vertical capacitor structure and a manufacturing method thereof to minimize the chip area occupied by the MIM capacitor structure.